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HL: Halbleiterphysik
HL 33: SiC
HL 33.4: Talk
Thursday, March 14, 2002, 11:15–11:30, H15
Traps at the interface of 3C-SiC MOS capacitors — •Florin Ciobanu1, Gerhard Pensl1, and Adolf Schöner2 — 1Lehrstuhl für Angewandte Physik, Universität Erlangen-Nürnberg — 2ACREO, Kista, Sweden
Heavily nitrogen-doped, free-standing 3C-SiC epilayers (200 µm thick) were used as a substrate for an homoepitaxial growth process (thickness of top epilayer = 10 µm). The net donor concentration of the 3C-SiC top layer was 3·1016 cm−3. Nominally dry oxidation was conducted at 1120∘C for 100 min leading to an oxide thickness of 75 nm. The oxide was annealed at the same temperature in Ar for 60 min. Conductance measurements taken on the MOS capacitors revealed an interface state density DIT of (3 to 4)·1011 eV−1cm−2 for states energetically located in the 3C-SiC band gap close to the conduction band edge. This value is 2 to 3 orders of magnitude lower than corresponding values for 4H-SiC MOS capacitors. In the middle of the band gap, DIT reaches maximum values of 1012 eV−1cm−2. The observed low DIT values and the high electron bulk mobility favor the 3C-SiC polytype for MOS device applications.