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HL: Halbleiterphysik
HL 10: Baulemente
HL 10.3: Talk
Monday, March 8, 2004, 15:45–16:00, H13
Patterning of sub 50 nm structures for diffusion investigations in vertical Double-Gate MOSFETs — •Jürgen Moers1, Stefan Trellenkamp1, Susan Kluth2, Patrick Kluth2, David Alvarez3,4, Johannes Kretz4, Siegfried Mantl1, and Hans Lüth1 — 1Institute of Thin Films and Interfaces, Forschungszentrum Jülich, D-52425 Jülich — 2Australien National University, Canberra, ACT 0200, Australia — 3IMEC, Kapeldreef 75, B-3001 Leuven, Belgium — 4Infineon Technologies AG, D-81730 Munich
The tremendous increase in computational efficiency was made possible by shrinking the dimension of microelectronic devices. This downsizing led to the well known Short Channel Effects (SCE). To account for these SCE the lateral layout was improved. For future CMOS applications this will be not sufficient, therefore new architectures must be investigated. One architecture is the Double-Gate-MOSFET, where the channel forming thin silicon layer is sandwiched between two gates; these two gates control the electric field in the silicon very efficiently and hence reduce SCE. Heart of this device is a silicon ridge of ∼20 nm width, in which the dopants are implanted. The channel length of the device is defined by the implantation energy and the diffusion during the subsequent thermal treatment. Therefore it is essential to investigate the diffusion in nanostructures.
Sub 50 nm structures in silicon were prepared using electron beam lithography and high selective reactive ion etching. First results show a different boron diffusion due to reduced transient enhanced diffusion. A qualitative interpretation of the effects are given.