Regensburg 2004 – scientific programme

Parts | Days | Selection | Search | Downloads | Help

HL: Halbleiterphysik

HL 10: Baulemente

HL 10.5: Talk

Monday, March 8, 2004, 16:15–16:30, H13

Simulation and fabrication of complementary tunneling transistors in silicon — •Peng-Fei Wang, Thomas Nirschl, Marcus Weis, Doris Schmitt-Landsiedel, and Walter Hansch — Institute for Technical Electronics, Technical University Munich, Arcisstr. 21, 80333 Munich, Germany

In this paper, a surface-tunneling transistor called TFET is fabricated using the CMOS compatible technologies. The gate controlled band-to-band tunneling is realized in this transistor. The gate controlled surface Esaki tunneling current is also observed at room temperature. Due to the distinct working principle of this novel transistor, the low sub-threshold leakage current and perfect drain current saturation can be obtained. Compared to the conventional NMOS, the lower leakage current and smaller Vth roll-off can be achieved. Since the impact ionization in this transistor is caused by the electrons injected from tunneling junction, TFET is also a hot electron transistor where the impact ionization can be controlled by the gate voltage. In addition, the complementary TEFT are fabricated on the same silicon substrate. The performances of the n-channel TFET and the p-channel TFET will be discussed in detail.