Berlin 2005 – wissenschaftliches Programm
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HL: Halbleiterphysik
HL 24: Bauelemente
HL 24.2: Vortrag
Samstag, 5. März 2005, 11:00–11:15, TU P-N229
Measurement of overlay accuracy of E-beam generated patterns for the fabrication of vertical gate all-around transistors — •Jürgen Moers, Andre van der Hart, and Hans Lüth — Institute of Thin Films and Interfaces and Center for Nanoelectronic Systems for Information Technology, Forschungszentrum Jülich, D-52425 Jülich
The scaling of MOSFET devices will go on at least for the next 15 years. This downsizing will lead to severe short channel effects, which have to be answered by new device architectures. The most promising candidates for end of roadmap MOSFETs are multigate devices such as FINFET, triple-Gate FET or vertical gate all-around FET. All of these MOSFETs show a proper control of the electric field in the channel area. However, for all these advanced MOSFETs, different patterns have to be aligned with an overlay accuracy of a few ten nanometers.
In this work, we present an overlay accuracy measurement method based on optical moire pattern: In three adjacent areas two overlaying gratings of period p1 and p2 are defined in two lithography steps: In the first area, the gratings are both defined in the first step, in the second area they are completely defined in the second step and in the third area p1 is defined in the first step and p2 in the second step. The three arising moire patterns have a phase difference according to their alignment shift: While the difference between the first and the second is due to statistical errors during the lithography (normally very small), the phase difference to the third area is attributed to the overlay error and hence a clear measure of it. The method is applied to a vertical gate all-around MOSFET process and overlay errors can be measured with an accuracy of less than 4nm.