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HK: Fachverband Physik der Hadronen und Kerne

HK 49: Poster

HK 49.30: Poster

Donnerstag, 15. März 2007, 16:00–17:00, P

FPGA-based highly parallel compute nodes — •Tiago Perez, Daniel Kirschner, and Ming Liu — II Physikalisches Institut, Heinrich-Buff-Ring 16, 35392, Gießen.

For the new proton antiproton annihilation experiment at Darmstadt, PANDA as well as for the planned upgrade of HADES, high data rates and sophisticated real time processing are foreseen. Thus, a general purpose compute node based on FPGA and modern network technologies is being designed in Gießen.
Each compute node will be equipped with four Virtex-4 family FPGAs, multiple gigabit Ethernet ports and optical links. The multiple network ports provide the bandwidth necessary to transport the large amount of data delivered by the detectors. The processing of data from nuclear physics experiments is, intrinsically, a parallel problem. Therefore the FPGA is the ideal technology to address the problem, because implicit parallelization can be implemented already in the block design stage.