Regensburg 2007 – scientific programme

Parts | Days | Selection | Search | Downloads | Help

DS: Fachverband Dünne Schichten

DS 11: Symposium: New Materials for Nanoelectronics

DS 11.4: Invited Talk

Tuesday, March 27, 2007, 11:00–11:30, H32

Advanced SOI CMOS transistors for high performance microprocessors — •Manfred Horstmann — AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany

An overview of state of the art advanced Silicon on Insulator CMOS transistors used for high performance microprocessors will be given. For advanced SOI transistors stress engineering has become a standard feature since the 90 nm technology node due to gate oxide scaling limitations [1]. Especially techniques to induce local strain like compressive and tensile stressed over-layer films, embedded-SiGe, and stress memorization are keys to maintain transistor performance. With optimization, the different stressors are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by ca. 50 % and 30 %, respectively. This results in 40 % higher product speed. In addition to reduce the lateral and vertical device dimensions advanced Laser or Flash) annealing has been applied [2]. These anneal processes yield an improved dopant activation for active and gate regions resulting in lower source-drain resistance and gate depletion without any additional diffusion. These techniques have been applied and optimized for 90 nm and 65 nm volume manufacturing and are scaleable to 45 nm design rules. Technology options for future transistors like Strained Silicon directly bonded on SOI, fully depleted SOI, High K or FinFETs will be discussed.

[1] M. Horstmann, et al., IEDM 2005, p. 243 [2] Th.Feudel et al., RTP Conference, Kyoto, 2006