Berlin 2008 – wissenschaftliches Programm

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DF: Fachverband Dielektrische Festkörper

DF 4: High-k dielectrics for highly scaled Silicon-based Micro- and Nanoelectronics

DF 4.1: Hauptvortrag

Montag, 25. Februar 2008, 14:00–14:40, EB 107

High-k gate dielectrics on silicon and on high-mobility semiconductors: Atomic-scale phenomena underlying transistor performance — •Martin M. Frank — IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598, USA

Computer chip technology is undergoing a materials revolution: Hafnium-based high-permittivity (`high-k') dielectrics are replacing the silicon oxide gate insulator in metal-oxide-semiconductor field-effect transistors (MOSFETs); and metals are replacing the polycrystalline silicon gate electrode. These changes allow us to extend the exponential increase in integration density and performance known as Moore's Law. Researchers are even attempting to replace the silicon channel itself by high-carrier-mobility semiconductors, such as germanium, III-V compounds, carbon nanotubes, or graphene.

I will provide an overview of the materials science underlying MOSFET performance. First, properties and scaling of the traditional silicon oxide insulator will be summarized. Then, focus will be on non-epitaxial Hf-, Al-, and Ti-based dielectrics on silicon and on high-mobility semiconductors. We describe how processing parameters determine stack structure, e.g. continuity of the high-k layer, interface composition, and oxygen vacancy concentration. Comparing Si to Ge and III-V substrates, differences in interface formation will be rationalized based on thermodynamic considerations. Finally, we illustrate how the stack structure determines device characteristics such as gate leakage, gate stack capacitance, threshold voltage, and carrier mobility.