Berlin 2008 – scientific programme

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DS: Fachverband Dünne Schichten

DS 27: Trends in Ion Beam Technology: From the Fundamentals to the Application

DS 27.3: Invited Talk

Thursday, February 28, 2008, 15:30–16:00, H 2013

Junction and Channel Engineering for Advanced Microprocessors — •Manfred Horstmann — AMD Saxony LLC & Co. KG, Wilschdorfer Landstraße 101, 01109 Dresden, Germany

An overview of state of the art Silicon on Insulator CMOS transistors used for 65 nm/45 nm volume manufacturing of multicore microprocessors will be given. AMDs unique technology and transistor progression model as well as the key challenges to increase the performance per watt of microprocessor products will be described. For advanced SOI transistors stress engineering has become a standard feature since the 90 nm technology node due to gate oxide scaling limitations [1]. Especially techniques which induce local strain such as compressive and tensile stressed over-layer films, embedded-SiGe, and stress memorization, are key to enhance transistor and product performance [2]. To reduce the lateral and vertical device dimensions advanced (Laser or Flash) annealing in combination with low energy implants has been applied [3]. These anneal processes yield an improved dopant activation for active and gate regions resulting in lower source-drain resistance and gate depletion without any additional diffusion. Starting with the 45nm node, reducing parametric scattering for instance by improving tilt, twist, energy etc. control of implant steps are an emerging topic for performance optimization. A novel technique to statistically investigate parametric scattering, directly in the microprocessor chip, will be presented.

[1] M. Horstmann, et al., IEDM 2005, p. 243 [2] A. Wei et al., VLSI 2007 [3] Th.Feudel et al., RTP Conference, Kyoto, 2006