Darmstadt 2008 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 5: Instrumentation und Anwendungen II

HK 5.1: Group Report

Monday, March 10, 2008, 14:00–14:30, 2D

ATCA Compliant Compute Nodes for HADES, PANDA and BESIII — •Tiago Perez¹, Camilla Gilardi¹, Xu Hao², Daniel Kirschner¹, Igor Konorov⁴, Andreas Kopp¹, Kris Korcyl⁵, Wolfgang Kühn¹, Johannes Lang¹, Jens Sören Lange¹, Ming Liu¹, Zhen’An Liu², Alexander Mann⁴, Da Peng², Johannes Roskoss¹, Lars Schmitt³, and Shuo Yang¹ for the HADES collaboration — ¹II. Physikalisches Institut, Univ. Giessen — ²IHEP Beijing — ³GSI Darmstadt — ⁴TU München — ⁵Jagiellonian University Krakow

FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. A single module supports an aggregate bandwidth of 30 GB/s featuring 8 optical links which are connected to RocketIO ports. Furthermore, four Gbit Ethernet links are available for easy connectivity to the PC world. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane. The system will be used to implement the trigger upgrade of the HADES and BESIII detector systems and will serve as a prototype platform for PANDA DAQ and triggering. The system is scalable and can be optimized for pipelined and parallel architectures. This work is supported in part by BMBF(6GI-179/6GI-180), BMBF-WTZ and GSI