Darmstadt 2008 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 5: Instrumentation und Anwendungen II

HK 5.7: Talk

Monday, March 10, 2008, 15:45–16:00, 2D

Design and implementation of a hierarchical DAQ network — •Norbert Abel¹, Frank Lemke², and Wenxue Gao² for the CBM collaboration — ¹KIP Heidelberg — ²University of Mannheim

The FAIR project comes with many new challenges. One of them is the data acquisition (DAQ) - the handling of the huge data streams produced by the detectors. DAQ can be partitioned into three major parts. Firstly, the different analog signals produced by one detector have to be digitalized and filtered. Secondly, the preprocessed data of several detectors has to be combined. And thirdly, the combined data has to be analyzed and stored. We are in a design process of such a three step DAQ for the STS (Silicon Tracker System). In our actual setup the first step is done by the so called FEE (Front End Electronic) containing the nXYTER, an ADC and the ROC (Read Out Controller). The nXYTER-Board is measuring the value and the exact time of a signal peak. This data has to be synchronized and the data not representing a signal peak has to be filtered out by the ROC. The FEE has multiple ways to pass the data. In our first test setup we did implement the Ethernet protocol, directly connecting the FEE with a PC running analyzing software. In future the FEE will be connected via optical fiber to Data Combiner Boards (DCB) and Active Buffer Boards (ABB) realizing the second step. The DCB with its multiple MGT's concentrates the data and presents a inner node of a hierarchical buildup. The ABB represents the data buffer and receiver for a root node. It is connected to a PC (via PCI Express), which is responsible for the third step.