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HL: Fachverband Halbleiterphysik

HL 1: III-V semiconductors I

HL 1.8: Vortrag

Montag, 23. März 2009, 12:15–12:30, BEY 81

III/V surface channel devices: substrate preparation, interface passivation and growth — •Mirja Richter¹, Chiara Marchiori¹, David J. Webb¹, Christian Gerl¹, Marilyne Sousa¹, Christophe Rossel¹, Caroline Andersson¹, Roland Germann¹, Heinz Siegwart¹, Edward Kiewra², Yanning Sun², Joel De Souza², Devendra Sadana², Thanasis Dimoulas³, and Jean Fompeyrine¹ — ¹IBM Zurich Research Laboratory, Rueschlikon, Switzerland — ²IBM Watson Research Center, Yorktown Heights, NY, USA — ³National Center for Scientific Research Demokritos, Athens, Greece

III/V-based metal-oxide-semiconductor field effect transistors (MOSFET) are considered as promising candidates for replacing Si-based devices at and beyond the 22 nm CMOS technology node. For their fabrication, it is essential to develop an effective surface passivation. Indeed, the presence of defects at the III/V-oxide interface introduces energy states in the gap which can pin the Fermi level. In addition, to profit from their intrinsic higher charge carrier mobility, high quality III/V channel deposition as well as surface preparation procedures are indispensable.

We will discuss MBE grown gate stacks with HfO2 dielectric and Si passivation layers. Structural characterization is accomplished by RHEED and in-situ X-ray photoelectron spectroscopy. Electrical properties of the stacks are studied by measurements performed on capacitors. By this means a minimum Si passivation layer thickness is determined. Data on long channel GaAs nFETs will also be presented.