Dresden 2009 – scientific programme

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HL: Fachverband Halbleiterphysik

HL 21: Devices

HL 21.1: Talk

Tuesday, March 24, 2009, 14:00–14:15, BEY 81

High-Performance Tunnel Field Effect Transistor (TFET) using ultra-high-k gate dielectrics — •Martin Schlosser, Helmut Lochner, Martin Sauter, Thomas Zilbauer, Torsten Sulima, and Ignaz Eisele — Institute of Physics, Nano and Micro Systems, University of the German Federal Armed Forces Munich, 85577 Neubiberg, Germany

Continuous downscaling of field effect transistors is about to reach physical limits and calls for new device concepts. The Tunnel FET (TFET), based on a gated pin-diode, is a promising candidate for future CMOS technology due to its superior properties like small subthreshold slope, fabrication without sophisticated technology and good temperature stability. However, increasing the on-current remains challenging. We propose to use thick ultra-high-k materials as gate dielectrics in order to induce a higher electric field at the tunnelling junction due to the well-known fringing field effect. While worsening the device characteristics of a conventional MOSFET, it turns out that this effect significantly enhances the device performance of TFET devices. The reason is that the off-current is given by a pin-diode leakage current, while the on-current increases exponentially with the electric field. On-currents fulfilling the actual ITRS roadmap and slopes down to 20 mV/dec are observed in simulations of the device by using a generic dielectric with k = 200 and d = 102 nm. As aggressive downscaling of EOT is not needed, the usability for high-frequency applications is very good due to the low gate capacitance.