Dresden 2009 – wissenschaftliches Programm
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HL: Fachverband Halbleiterphysik
HL 21: Devices
HL 21.2: Vortrag
Dienstag, 24. März 2009, 14:15–14:30, BEY 81
Separation and Analysis of different leakage mechanisms in modern MOSFETs — •Guntrade Roll1, Matthias Goldbach2, Andre Wachowiak2, Juergen Holz2, and Lothar Frey3 — 1Namlab Gmbh, D-01187 Dresden — 2Qimonda, D-01099 Dresden — 3Fraunhofer IISB, D-91058 Erlangen
CMOS device development via gate length reduction is driven by the requirement for performance enhancement under power consumption control. Gate length scaling is enabled by reducing gate oxide thickness, parasitic capacitances as well as source/drain junction depth. These actions typically lead to increasing device leakage currents.
I will present detailed investigations of leakage currents and mechanisms on industry fabricated PFET devices with channel length smaller 100nm. The influence of the gate induced drain leakage (GIDL), drain induced barrier lowering (DIBL), p+/n-junction- and gate leakage on the total device current loss is studied with temperature dependent current-voltage- and capacitance-voltage-measurements. Two types of sample systems have been investigated:
- PFETs with ultra shallow source/drain (carbon co-implantation)
- PFETs with high-k gate dielectric and metal gate
The analysis reveals the relative magnitude of the different leakage current contributions, the DIBL effect and GIDL control the leakage for increasing drain bias. The underlying mechanisms (direct tunneling, defect assisted etc.) are investigated.