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T: Fachverband Teilchenphysik

T 58: Halbleiterdetektoren 4

T 58.7: Talk

Thursday, March 12, 2009, 18:15–18:30, A125

Simulation of the Digital Architecture of the New ATLAS Pixel Front-End IC for Upgraded LHC — •David Arutinov, Marlon Barbero, Volker Büscher, Tomasz Hemperek, and Norbert Wermes — Physikalisches Institut Universität Bonn

ATLAS is one of the four main particle experiments located on the LHC in CERN. To provide excellent single point resolution, the innermost part of ATLAS consists of a pixel detector. Located at a radius of  5cm, the inner layer of the pixel detector is placed in a very harsh radiation environment. Due to radiation damage, this layer needs replacement before the 10-fold luminosity upgrade of the LHC -so-called sLHC- foreseen around 2016-1018. A long shutdown planned for an intermediate luminosity upgrade in 2012-2013 provides a good opportunity for the insertion of a smaller radius inner-layer. The current pixel Front End (FE-I3) is designed to survive several years of nominal LHC luminosity but would become inefficient for this new layer at the higher luminosity that will be reached before the sLHC phase. Thus a new chip called FE-I4 is needed to cope with the new conditions. FE-I4 targets both the needs of the new inner layer for the intermediate upgrade, and the needs of the outer layers of the pixel detector at sLHC. A prototype FE-I4 consisting of an analog pixel array and many peripheral blocks already exists. The main focus has now shifted to the design of the corresponding digital FE part and overall digital FE architecture. To this purpose, a high level C++ simulation has been developed. Results of this work on the digital structure of the new IC will be presented in this talk.