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T: Fachverband Teilchenphysik

T 58: Halbleiterdetektoren I

T 58.4: Vortrag

Montag, 15. März 2010, 17:30–17:45, HG VI

FE-I4, the New ATLAS Pixel Chip for Upgraded LHC Luminosities — David Arutinov, •Marlon Barbero, Markus Gronewald, Tomasz Hemperek, Michael Karagounis, Hans Krueger, Andre Kruth, and Norbert Wermes — Physikalisches Institut der Universität Bonn, Nussallee 12, D-53115 Bonn

The new ATLAS pixel chip FE-I4 is being developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project and the outer pixel layers of Super-LHC. FE-I4 is designed in a 130 nm CMOS technology and is based on an array of 80x336 pixels, each 50x250 μm2 and consisting of analog and digital sections. The analog pixel section is designed for low power consumption. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides a handle to the problem of timewalk. The chip periphery contains a digital control block, a command decoder, powering blocks, a data reformatting unit, an 8b10b coder and a clock multiplier unit, which handles data transmission up to 160 Mb/s for the IBL. Increased power consumption in the inner layers of ATLAS translates into more material for cooling and power routing, which degrades the tracking and the b-tagging quality. As a consequence the FE-I4 collaboration places severe constraints on the power consumption of all blocks. First full scale FE-I4 submission will occur beginning 2010.