Bonn 2010 – scientific programme

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T: Fachverband Teilchenphysik

T 62: Halbleiterdetektoren V

T 62.8: Talk

Friday, March 19, 2010, 15:45–16:00, HG VI

Module Concepts with (Ultra-) Thin Chips for ATLAS IBL and sLHC — •Laura Gonella, Marlon Barbero, Fabian Hügging, Hans Krüger, Walter Ockenfels, Wolfgang Dietsche, and Norbert Wermes — Physikalisches Institut der Universität Bonn, Nußallee 12, D-53115 Bonn

Material budget is a crucial issue in vertex detectors for High Energy Physics experiments. For the Insertable B-Layer (IBL) project, a new front-end chip (FE-I4) is designed with an area of 18.8 x 20.2 mm2, almost 5 times larger than the present FE chip (FE-I3). A thickness of 300 to 350 μm would be required to avoid bending of this large chip at the high temperatures used in a standard flip-chip process, leading to a significant contribution of the chip to the material budget. A new flip-chip process is thus under development with IZM Berlin to allow for flip-chip using FE-I4 chips thinned down to about 100 μm. Results on flip-chip assemblies of 90 μm thin 2x2 FE-I3 dies to dummy sensors are encouraging, showing only some small issues that could be solved with minor process modifications or with slightly thicker chips. Both possibilities are studied to reach the goal of having thinned down FE-I4 to 100-200 μm. Bumped thin chips will also enable usage of Through Silicon Vias (TSV) in pixel modules. TSV is a via-last 3D integration technique which allows routing of signals on the backside of the FE. Two different types of vias are studied, Straight Side Walls and Tapered Side Wall. The development of a module with Tapered Side Wall TSV and simple backside metallization connected to a flex hybrid has started with IZM Berlin.