Regensburg 2010 – scientific programme

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DF: Fachverband Dielektrische Festkörper

DF 6: Focus Session: High-k and high mobility materials for CMOS

DF 6.4: Invited Talk

Tuesday, March 23, 2010, 11:35–12:15, H11

Aspect Ratio Trapping: A Heterointegration Solution for Ge and III-V CMOS — •James Fiorenza — AmberWave Systems, Salem, NH, USA

Enhanced MOSFETs using high mobility non-silicon channel materials are being intensively investigated for future CMOS nodes. This research path is extremely promising, but significant challenges remain. Perhaps the largest challenge is the heterointegration of the high mobility materials with silicon. A heterointegration technique called Aspect Ratio Trapping (ART) is well suited to the unique integration requirements of mobility-enhanced CMOS. This technique involves epitaxial growth in narrow (< 500 nm), high aspect ratio silicon dioxide trenches. Threading dislocations generated by the lattice mismatch between the epitaxial material and silicon are trapped by the sidewalls of the trenches, greatly reducing the surface dislocation density. This technique been shown to be effective with a variety of relevant cubic semiconductors including Ge, InP and GaAs. The resulting buffer layers can be thinner than 500 nm, more than an order of magnitude thinner than traditional graded buffer heterointegration approaches, a critical advantage for CMOS applications.