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HL: Fachverband Halbleiterphysik
HL 10: Devices II
HL 10.2: Talk
Monday, March 22, 2010, 14:15–14:30, H13
Dot-Field Effect Transistor: Using locally strained silicon for MOSFET applications — •Jürgen Moers1, Julian Gerharz1, Gregor Mussler1, Cleber Biasotto2, Vladimir Jovanovic2, Lis Nanver2, and Detlev Grützmacher1 — 1Institute for Bio and Nanosystems, Research Centre Jülich, D-52425 Jülich, Germany — 2DIMES, TU Delft, Mekelweg 4, 2628 CD Delft, The Netherlands
Typical dimensions of electronic devices have been scaled into the sub-50nm range. The use of trained silicon for carrier mobility enhancement is a route to meet the challenges occurring at those dimensions. By means of templated self assembly of SiGe-dots on prepatterned substrates and epitaxial overgrowth a silicon layer is created, which is strained on top of the SiGe-dots and their near vicinity. Integrating the MOSFET on the dot will use the strain to improve the device performance.
During processing special emphasis has to be laid on the overlay accuracy and low thermal budget processing to prevent intermixing of the strained silicon layer with the SiGe-dot. While the gate dielectric was deposited by CVD the activation of dopants was done by laser annealing.
DotFET devices with gate lengths between 50 and 200 nm and gate widths between 100 and 300 nm were fabricated with 15 nm SiON as gate dielectric. First measurements show an improved current drivability in respect to reference devices processed on the same wafer, indicating the suitability of this device concept. Further improvements can be reached by removing the SiGe-dot from beneath the gate.