Bereiche | Tage | Auswahl | Suche | Downloads | Hilfe

HL: Fachverband Halbleiterphysik

HL 10: Devices II

HL 10.4: Vortrag

Montag, 22. März 2010, 14:45–15:00, H13

Interface Defect Study by GIDL Current and Charge Pumping Measurements on MOSFET Devices — •Guntrade Roll¹, Stefan Jakschik¹, Andre Wachowiak², Matthias Goldbach², and Lothar Frey³ — ¹Namlab gGmbh, D-01187 Dresden — ²Qimonda, D- 01099 Dresden — ³Fraunhofer IISB, D-91058 Erlangen

The continued improvement in CMOS technology requires the scaling of transistor dimensions while maintaining acceptable leakage currents. One key to performance enhancement is a good process control of the gate oxide to silicon interface properties, such as a low defect density and reduced oxide regrowth. The Gate Induced Drain leakage (GIDL) enhances power consumption when the gate is turned off. The GIDL current increases as the interface oxide thickness is reduced, due to electric field increase. Another factor which varies the GIDL leakage is the interface trap density at the gate edge.

We report the investigation of two types of samples. First the dependence of the interface traps on the carbon content in the ultra shallow Source/Drain junction of PFETs is evaluated using a lateral profiling Charge Pumping technique. The electrical measurements reveal an increase of GIDL current by carbon co-implantation.

In the second set of samples the spacer material and the gate etch parameters of devices with high-k dielectric are varied. This reduces the interface oxide regrowth and decreases the GIDL current. We present a correlation between GIDL current and Charge Pumping measurements and compare both the influence of the electric field and the interface trap density on the leakage.