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HL: Fachverband Halbleiterphysik

HL 10: Devices II

HL 10.7: Vortrag

Montag, 22. März 2010, 15:30–15:45, H13

VLS-grown Vertical Silicon Nanowire FETs — •Hesham Ghoneim, Mikael Bjoerk, Heinz Schmid, Kirsten Moselund, Siegfried Karg, Walter Riess, and Heike Riel — IBM Research GmbH, IBM Research Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland

Owing to their potential compatibility with existing CMOS technology, silicon (Si) nanowires (NWs) are considered to be one of the most promising candidates for future logic and memory elements. A major advantage is the significantly improved gate control using a Gate-All-Around (GAA) structure offered by the NW geometry allowing further downscaling beyond the 22nm node.[1] We report on the fabrication and characterization of vertical Field Effect Transistors (FETs) and vertical impact-ionization FETs based on Vapor-Liquid-Solid (VLS) grown Si NWs. Taking advantage of the vertical epitaxial VLS growth of Si NWs we fabricate GAA devices in a vertical geometry. For source and drain doping we investigated several approaches: in-situ doping during VLS-growth, ion implantation and solid source diffusion doping for both n- and p-type doping. With these methods n-i-n, p-i-p and n-i-p vertical nanowire structures are fabricated and used as basis for p-FETs, n-FETs and impact-ionization FETs. Electrical characteristics of the devices are investigated and a comparison between the different approaches and structures will be discussed.

[1]J.-P. Colinge, Multiple-gate SOI MOSFETs, Solid-State Electronics, 2004, Vol. 48, pp. 897-905.