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HL: Fachverband Halbleiterphysik

HL 61: Poster II: Materials, Interfaces and Heterostructures

HL 61.9: Poster

Donnerstag, 25. März 2010, 18:00–20:00, Poster D1

Investigation of top gates with ALD deposited dielectric on graphene structures — •Franz-Xaver Schrettenbrunner, Dieter Weiss, and Jonathan Eroms — Institut für Experimentelle und Angewandte Physik, Universtität Regensburg, 93040 Regensburg

We report the fabrication and transport measurements of top gated mono- and bilayer graphene devices. The insulating Al₂O₃ top gate was realized using atomic layer deposition (ALD). With a TMA/water process at 100 ^∘C we could achieve complete coverage of the graphene flakes and produce stable gates with a thickness down to 30nm. In particular, using both the aluminum oxide top gate and the 300nm SiO₂ backgate on our Si-chip, we were able to create a gate-induced insulating state in bilayer graphene. Using a model which regards the two layers as electrically decoupled, we could determine the density of background impurities and on which of the two layers they were preferentially located.