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HL: Fachverband Halbleiterphysik

HL 85: Poster Session II

HL 85.102: Poster

Donnerstag, 17. März 2011, 18:00–21:00, P4

Geometry effects on Coulomb charging in CMOS-compatible SOI-SETs — •Matthias Ruoff¹, Dharmraj Kotekar-Patil¹, Stefan Jauerneck¹, David Wharam¹, Dieter Kern¹, Marc Sanquer², and Maud Vinet³ — ¹Eberhard Karls Universität, Tübingen — ²CEA INAC, Grenoble, France — ³CEA LETI, Grenoble, France

The charging energy of a single electron transistor (SET) and therefore its suitability for high-temperature operation is determined by the effective size of the Coulomb island. Nanowire SOI-FETs with nominally undoped channels of different widths and thicknesses and various gate lengths, fabricated in the FP7 project AFSID with a CMOS compatible process, have been investigated. In this case the Coulomb island may be formed by a small body of undoped silicon, a single stray dopant from source/drain implantation, or one or more dopant atoms in the access regions of the channel. The investigated devices show clear Coulomb blockade oscillations. From their period the gate capacitance can be directly obtained. Gate efficiency and total capacitance can be extracted by fitting theoretical models to conductance peak shapes and from charge stability diagrams. Capacitances resulting from different geometrical models are compared with those obtained from the transport measurements.