Berlin 2012 – scientific programme
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DS: Fachverband Dünne Schichten
DS 29: High-k and low-k dielectrics (joint session with DF)
DS 29.2: Talk
Wednesday, March 28, 2012, 09:50–10:10, EB 407
Bilayer gate dielectric stacks of cerium oxide and titanium oxide for nanoelectronics — •Meng Meng Vanessa Chong1, 2, Kam Chew Leong2, Pooi See Lee1, and Iing Yoong Alfred Tok1 — 1School of Materials Science and Engineering, Nanyang Technological University, Block N4.1, Nanyang Avenue, Singapore 639798 — 2Global Foundries Singapore Pte. Ltd., Singapore 528830
Numerous materials systems are under consideration as potential replacements for SiO2 as the gate oxide material for sub-0.1 micron CMOS technology. Many properties have to be considered in selecting a suitable material because of emerging issues with high-k technology development. Though, many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all the required properties.
This work focuses on the rare earth oxide - CeO2 as alternative dielectric as it has small lattice mismatch with Si and high k-values. This study also shows the integration of a high-k passivation layer (TiO2) to suppress the formation of undesirable interfacial layer. Physical characterizations are done to determine the stoichiometry, surface roughness and interface quality.
In addition, temperature dependent measurements are done to identify the different conduction mechanisms such as Poole-Frenkel emission. Identification of various leakage constituent is important for estimation and reduction of leakage power. Furthermore, in-depth electrical analysis helps to determine the quality of the film and dielectric interface.