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HK: Fachverband Physik der Hadronen und Kerne

HK 53: Poster – Instrumentation

HK 53.10: Poster

Donnerstag, 22. März 2012, 14:00–16:00, P Foyer

Implementation of a High Resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array — Cahit Ugur¹, Eugen Bayer², Nikolaus Kurz³, •Jan Michel⁴, and Michael Traxler³ — ¹Helmholtz-Institut Mainz, Johannes Gutenberg-Universität Mainz, Mainz, Germany — ²Department for Digital Electronics, University Kassel, Kassel, Germany — ³GSI Helmholtz Centre for Heavy Ion Research, Darmstadt, Germany — ⁴Institute for Nuclear Physics, Goethe University Frankfurt, Frankfurt, Germany

A high resolution time-to-digital converter (TDC) was implemented in a general purpose field-programmable gate array (FPGA), a re-programmable digital chip. RMS and the time resolution of different channels are calculated for one clock cycle (5 ns) interval and a minimum of 10.3 ps RMS on two channels is achieved, which yields to a time resolution of 7.3 ps (10.3 ps/√2) on a single channel. The TDC can be used in time-of-flight, time-over-threshold, drift time measurement applications as well as many other measurements with specific Front-End Electronics (FEE), e.g. charge measurements with charge-to-width (Q2W) FEE. The re-programmable flexibility of FPGAs also allows to have application specific features, e.g. trigger window, zero dead time etc.