Dresden 2013 – scientific programme
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T: Fachverband Teilchenphysik
T 76: DAQ, Trigger und Elektronik 1
T 76.8: Talk
Wednesday, March 6, 2013, 18:35–18:50, GER-039
A Topological Processor Prototype for the ATLAS Level-1 trigger upgrade — Bruno Bauss, Volker Büscher, Reinhold Degele, Patric Kiese, Andreas Reiss, Ulrich Schäfer, •Eduard Simioni, Stefan Tapprogge, and Volker Wenzel — Johannes Gutenberg Universität, Staudingerweg 7, 55128, Mainz
Event Triggering and Data Acquisition is one of the extraordinary challenges faced by the ATLAS detector at the high luminosity LHC col- lider. Multiple events occur at the beam crossing frequency of 40 MHz, but only about 200-350 events per second can be written to disk. Start- ing in 2015 the Large Hadron Collider will collide proton bunches at the nominal energy of 14 TeV with an increased instantaneous luminosity up to 3×1034 cm−2s−1. The resulting higher event rate will challenge the existing ATLAS trigger system. To keep the trigger effciency high despite the increased event rate, a new electronics module is foreseen to be added in the Level-1 Calorimeter Trigger: the Topological Processor (L1Topo).
From a hardware point of view, L1Topo requires high density opti- cal I/O and high bandwidth, achieved by adopting the state-of-the-art FPGAs with embedded Multi-Gb/s transceivers and high density Multi- Gb/s opto converters. With L1Topo it will be possible for the first time to concentrate detailed information from subdetectors into a single module. Information on angles between jets and/or leptons can be used to reduce the Level-1 trigger rates by means of specific topological algorithms and to produce an output within the Level-1 trigger latency budget of 2.5 µs. This talk will present the hardware design of the L1Topo prototype and several crucial tests on high speed links and data transmission latency