Frankfurt 2014 – wissenschaftliches Programm

Bereiche | Tage | Auswahl | Suche | Aktualisierungen | Downloads | Hilfe

HK: Fachverband Physik der Hadronen und Kerne

HK 34: Instrumentierung

HK 34.4: Vortrag

Mittwoch, 19. März 2014, 17:45–18:00, HZ 8

Implementation of the FPGA-based cluster finder for the CBM-MVD — •Qiyan Li for the CBM-MVD collaboration — Goethe-University, Frankfurt

The Micro Vertex Detector (MVD) of the CBM experiment at FAIR is optimized to identify rare open-charm particles by their decay topology, which requires a high demands on its spatial resolution, radiation hardness and rate capability. The MVD will be equipped with CMOS Monolithic Active Pixel Sensors. Those sensors feature an on-chip zero suppression and 1-dimensional cluster finding.
To further reduce the load on the event builders and future mass storage systems, we have developed a 2-dimensional cluster finding and characterization algorithm suited for preprocessing and reducing the data streams generated by the free-running pixel sensors. The algorithms are implemented in the FPGA of the readout controller system (ROC) for the MVD. After the sensors’ data are cross-checked for possible errors and synchronization problems, they will be stored in a frame buffer, which serves as the input for the cluster finder. Then, the output of cluster finder will be transferred to a readout buffer and shipped forward via TRB-net.
This contribution will present the implementation of the algorithms on the remaining free resources of the FPGAs in the MVD ROCs, followed by presenting test result on compression capability, performance and error-handling. * supported by BMBF (05P12RFFC7), HIC for FAIR, and GSI.