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HK: Fachverband Physik der Hadronen und Kerne
HK 57: Instrumentierung
HK 57.6: Vortrag
Freitag, 21. März 2014, 12:30–12:45, HZ 9
FPGA helix tracking algorithm for PANDA — •Yutie Liang1, Martin Galuska1, Thomas Gessler1, Jifeng Hu1, Wolfgang Kühn1, Jens Sören Lange1, David Münchow1, Björn Spruck1, and Hua Ye1,2 for the PANDA collaboration — 1II. Physikalisches, Giessen University, 35392, Germany — 2Institute of High Energy Physics, Beijing 10049, P. R. China
The PANDA detector is a general-purpose detector for physics with high luminosity cooled antiproton beams, planed to operate at the FAIR facility in Darmstadt, Germany. The central detector includes a silicon Micro Vertex Detector (MVD) and a Straw Tube Tracker (STT). Without any hardware trigger, large amounts of raw data are streaming into the data acquisition system. The data reduction task is performed in the online system by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays) as first level and on a farm of GPUs or PCs as a second level. One important part in the system is the online track reconstruction. In this presentation, an online tracking finding algorithm for helix track reconstruction in the solenoidal field is shown. A performance study using C++ and the status of the VHDL implementation will be presented.
*This work was supported in part by BMBF (05P12RGFPF), the LOEWE-Zentrum HICforFAIR and the JCHP FFE(COSY-099).