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T: Fachverband Teilchenphysik

T 71: DAQ, Trigger, Elektronik 3

T 71.3: Vortrag

Dienstag, 25. März 2014, 17:15–17:30, GFH 01-731

Upgrade of the ATLAS Level-1 trigger with an FPGA based Topological Processor — Bruno Bauss, Volker Büscher, Regina Caputto, Reinhold Degele, Katharina Jakobi, Christian Kahra, Andreas Reiss, Jan Schäffer, Ulrich Schäfer, •Eduard Simioni, Manuel Simon, Stefan Tapprogge, Pedro Urrejola, Alexander Vogel, and Markus Zinser — Staudingerweg 7, Uni Mainz

The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC).

LHC proton collision at a frequency of 40 MHz, requires a trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz.

Due to the increase in the LHC instantaneous luminosity in 2015, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo).

The L1Topo receive data in a dedicated format from the calorimeters and muon detectors to be processed into specific topological algorithms. Those algorithms sits in high-end FPGAs to perform geometrical cuts, correlations and calculate complex observables as the invariant mass.

The output of such topological cuts is sent to the Central Trigger Processor (CTP). Since the Level-1 trigger it’s a fixed latency pipelined system the main requirement for the L1Topo is a large input bandwidth (about 1Tb/s), optical connectivity and low processing latency on the Real Time data path.

This presentation focuses on the design, test and commissioning at CERN of the L1Topo final production module.