Wuppertal 2015 – scientific programme

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T: Fachverband Teilchenphysik

T 61: DAQ

T 61.8: Talk

Wednesday, March 11, 2015, 18:30–18:45, G.10.07 (HS 5)

Boundary Scan Test of Belle II Pixel Detector Electronics — •Philipp Leitl — Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, 80805 München

For the upgrade of the Vertex Detector at the Belle II experiment, DEPFET sensors will be used. These sensors need Application-Specific Integrated Circuits (ASICs) for control, readout and data processing. Because of high demands for a low material budget in the sensitive area, there is only little space left for these ASICs. Using state-of-the-art technologies like Ball Grid Array (BGA) chips, which are flip-chip mounted, the requirement of 14 ASICs on each of the 40 half ladders can be fulfilled.

However, this highly integrated on-sensor ASIC solution results in a lack of physical access to the electrical connections, which is a problem for traditional testing methods. To overcome these limitations, the JTAG standard IEEE 1149.1 is used to check if the circuit is in working condition. This method provides electrical access to the boundary scan cells implemented in the ASICs. Therefore it is possible to perform connectivity tests and verify if the production of the circuit was successful.