Darmstadt 2016 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 29: Instrumentation VII

HK 29.3: Talk

Tuesday, March 15, 2016, 17:00–17:15, S1/01 A2

A test system for electronics components of the PANDA MVD. — •Alessandra Lai, Tobias Stockmanns, and James Ritman for the PANDA collaboration — Forschungszentrum Juelich

The PANDA experiment is one of the main devices at the upcoming Facility for Antiproton and Ion Research(FAIR), under construction in Darmstadt, Germany. This fixed target experiment will study the transition region between perturbative and non-perturbative QCD in the energy regime of the charmonium. The innermost sub-detector system of the target spectrometer of the PANDA experiment is the Micro Vertex Detector(MVD). Two types of silicon detectors will be used: pixel detectors and double-sided strip detectors. Two front-end chips are required: the Torino Pixel ASIC(ToPix) and the PANDA Strip ASIC(PASTA). Both are designed to transmit data at a rate of several hundred Megabits per second and are capable of handling the expected hit rate in hot spots of the detector. One key component in the development of new front-end electronics is a test system capable to handle these high rates. It should be flexible enough to test different kinds of front-end electronics and it should be easy to adapt to new prototypes. Therefore, an FPGA-based system is the ideal candidate. For this test system suitable firmware and a software framework are needed. Such a system is under development at the Forschungszentrum Jülich. The main component of the Jülich Digital Readout System(JDRS) is a Virtex 6 FPGA on a development board from Xilinx.

In this talk, the mentioned read-out system will be introduced and lab tests with the front-end electronics of the MVD will be presented.