Darmstadt 2016 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 60: Instrumentation XVII

HK 60.8: Talk

Thursday, March 17, 2016, 18:15–18:30, S1/01 A4

Implementation of the ALICE HLT hardware cluster finder algorithm in Vivado HLS — •Frederik Grüll, Heiko Engel, and Udo Kebschull for the ALICE collaboration — Infrastructure and Computer Systems in Data Processing, Goethe University Frankfurt, Germany

The FastClusterFinder algorithm running in the ALICE High-Level Trigger (HLT) read-out boards extracts clusters from raw data from the Time Projection Chamber (TPC) detector and forwards them to the HLT data processing framework for tracking, event reconstruction and compression. It serves as an early stage of feature extraction in the FPGA of the board. Past and current implementations are written in VHDL on reconfigurable hardware for high throughput and low latency. We examine Vivado HLS, a high-level language that promises an increased developer productivity, as an alternative. The implementation of the application is compared to descriptions in VHDL and MaxJ in terms of productivity, resource usage and maximum clock frequency.