Münster 2017 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 16: Instrumentation IV

HK 16.3: Talk

Tuesday, March 28, 2017, 12:00–12:15, F 072

ALICE HLT readout and FPGA based data processing in Run 2 — •Heiko Engel and Udo Kebschull for the ALICE collaboration — IRI, Goethe-Universität Frankfurt

The ALICE High Level Trigger (HLT) is a computing cluster dedicated to the online reconstruction, analysis and compression of experimental data. The High-Level Trigger receives detector data via serial optical links into custom PCI-Express based FPGA readout cards installed in the cluster machines. The readout cards provide the data to the host machines via Direct Memory Access (DMA). Raw data from the Time Projection Chamber (TPC) is processed already in the FPGA with a hardware cluster finding algorithm. This implementation is significantly faster than a software implementation and saves a great amount of CPU resources in the HLT cluster. It also provides some data reduction while introducing only a marginal additional latency into the readout path. This algorithm was ported to the new HLT readout hardware for Run 2, was improved for higher link rates and adjusted to the upgraded TPC Readout Control Unit (RCU2). A flexible firmware implementation allows both the old and the new TPC data format and link rates to be handled transparently. Extended protocol and data error detection, error handling and the enhanced RCU2 data ordering scheme provide an improved physics performance of the cluster finder. This contribution describes the state of the firmware developments in the HLT, the integration of the readout into the HLT framework as well as the FPGA based TPC cluster finding and its adoption to the changed readout conditions during Run 2.