Münster 2017 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 45: Instrumentation X

HK 45.2: Talk

Thursday, March 30, 2017, 14:15–14:30, F 072

An FPGA based Pre-Processor for the ALICE TPC Readout Upgrade — •Sebastian Klewin for the ALICE collaboration — Physikalisches Institut, Universität Heidelberg

After the major upgrade of ALICE for Run 3 of the Large Hadron Collider at CERN, the new frontend electronics of the Time Projection Chamber (TPC) will generate around 4 TB/s of raw data. This enormous amount of information can not be written and stored on disc and thus has to be processed and reduced online.

As the first processing step, a cluster finding will be performed on the data directly in the readout electronics. Looking for charge clusters already at this early stage of the readout provides the opportunity to use non zero-suppressed data which increases the sensitivity and resolution especially for small clusters. For this purpose, a 2D cluster finder is developed for and implemented in an FPGA. The high number of channels which have to be processed within a single FPGA makes this development challenging. The conceptual layout of such a cluster finder algorithm will be presented as well as first simulation results.