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T: Fachverband Teilchenphysik

T 46: Elektronik

T 46.1: Vortrag

Dienstag, 28. März 2017, 11:00–11:15, JUR 5

KLauS: A low power Silicon Photomultiplier Charge Readout ASIC in 0.18um UMC CMOS Technology — •Konrad Briggl for the CALICE-D collaboration — KIP, Universität Heidelberg

The CALICE collaboration is developing highly granular calorimeters fur future linear collider experiments. The high channel count, as well as the little space for cooling infrastructure, pose stringent requirements on the integrated readout electronics, limiting the allowed power consumption to 25uW per channel by the use of powergating techniques. We present the development of KLauS, a low power mixed mode ASIC for charge readout of Silicon Photomultipliers (SiPMs). The analog front-end is designed to achieve sufficient signal to noise ratio for single pixel signals using novel low-gain SiPMs, while allowing charge measurements over the full dynamic range of these sensors. It consists of an input stage, two charge measurement branches and a fast comparator for timestamping and autotriggered operation. A successive approximation register (SAR) ADC with a resolution of 10bits was implemented to digitize the pulse height informations. An additional pipelined SAR stage allows to increase the quantization resolution to 12bit in order to digitize single pixel charge spectra. Characterization measurements and design details of a 7 channel mixed signal prototype ASIC will be presented.