Münster 2017 – wissenschaftliches Programm
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T: Fachverband Teilchenphysik
T 94: Pixeldetektoren 4
T 94.5: Vortrag
Mittwoch, 29. März 2017, 17:45–18:00, VSH 116
FE65-P2: A prototype pixel readout chip in 65nm technology for HL-LHC upgrades — Rebecca Carney2, Markus Cristinziani1, Mauricio Garcia-Sciveres2, Dario Gnani2, •Carlo Alberto Gottardo1, Timon Heim2, Tomasz Hemperek1, Lashkar Kashif3, Hans Krüger1, Abderrezak Mekkaoui2, Veronica Wallagen2, and Norbert Wermes1 — 1Physikalisches Institut, Universität Bonn — 2Lawrence Berkeley National Lab, Berkeley, CA, USA — 3University of Wisconsin-Madison, Madison, WI, USA
The High-Lumi LHC upgrade of the trackers of the ATLAS and CMS experiments is a challenging benchmark for silicon detector technology. High rate, radiation hardness, low noise and low power consumption are the main concerns the detector design has to deal with.
The FE65-P2 pixel readout test chip has been developed by the RD53 collaboration with the goal of demonstrating small (50 µm pitch) pixel performance and validating its layout scheme in 65 nm technology. The layout design, dubbed "analog island in a digital sea" is characterized by analog front-end blocks shared by four pixels and surrounded by synthesized digital logic and it nominally operates down to a threshold of 500 electrons.
A description of the readout chip and total ionizing dose (TID) radiation hardness test will be presented.
Several parameters of the chip have been measured during x-ray irradiation up to a dose of 45 Mrad showing both expected and unexpected features.