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T: Fachverband Teilchenphysik

T 27: Halbleiterdetektoren II

T 27.7: Vortrag

Dienstag, 26. März 2019, 17:30–17:45, H03

Design of HVCMOS pixel sensor chips for ATLAS ITk upgrade — Mridula Prathapan and •Rudolf Schimassek — Karlsruhe Institute of Technology, Karlsruhe, Germany

The high voltage CMOS (HVCMOS) pixel sensors are designed to meet the specifications for the outer pixel layers ATLAS ITk. The HVCMOS prototypes are large fill factor designs in 180nm process on high resistivity substrates. The readout architecture is crucial for achieving high detection efficiencies for high particle hit rates such as 2 MHz/mm² in the outer layers of the ITk pixel tracker. The first generation (0.33 cm × 1.3 cm) HVCMOS prototype ATLASpix1_M2 featured a triggered readout scheme with parallel hit transfer from pixels to hit buffers (pptB) and Content Addressable Buffer readout (CAB). Various laboratory tests and irradiation studies have been conducted on ATLASpix1_M2 and is proven to be working. ATLASpix2 is a (3.7 mm × 4.2 mm) MPW run which is optimized for better time resolution and faster readout than its predecessor ATLASpix1_M2. Three novel design concepts namely, programmable sorted readout, hit neighbour logic and smart pixel grouping are introduced in ATLASpix2. Several design improvements are made for ATLASpix3, which is 2×2 cm². ATLASpix3 will be used for construction of the HVCMOS demonstrator quad module. This work presents the design evolution of ATLASpix chips in detail together with some measurement results.