Aachen 2019 – wissenschaftliches Programm

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T: Fachverband Teilchenphysik

T 43: DAQ und Trigger II

T 43.7: Vortrag

Dienstag, 26. März 2019, 17:30–17:45, S06

Development of serial data link IC in 65nm CMOS for the RD53B HL-LHC pixel readout chip — Tomasz Hemperek, Hans Krüger, Konsantinos Moustakas, •Piotr Rymaszewski, Marco Vogt, Tianyang Wang, and Norbert Wermes — Physikalisches Institut Universität Bonn, Bonn, Germany

The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Due to similar requirements ATLAS and CMS are working together within RD53 collaboration on a design of a pixel readout chip in 65nm CMOS technology to be used for the LHC Phase-II upgrade. This talk presents the I/O interface of this readout chip, focusing especially on some timing-critical circuit blocks: CDR (Clock Data Recovery), serializer and CML (Current Mode Logic) output driver. The CDR recovers clock from 160 Mbps incoming data stream and produces 1.28 GHz clock to be used by the serializer. The double data rate serializer combines 20 data streams into a single 1.28 Gbps stream, which is send off-chip by a CML driver. Circuit description together with measurement results will be presented including jitter performance, startup reliability and radiation hardness.