München 2019 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 8: Instrumentation II

HK 8.6: Talk

Monday, March 18, 2019, 15:15–15:30, HS 12

High-Level Synthesis in Algorithm Implementation and Data Preprocessing on FPGAs — •Thomas Janson and Udo Kebschull — IRI, Goethe-Universität Frankfurt am Main, Senckenberganlage 31, 60325 Frankfurt am Main, Germany

In this talk, we discuss the high-level synthesis methodology from Xilinx to implement algorithms on FPGAs. The idea is to use a C++ high-level language to program an algorithm for an implementation in a massive parallel fashion, where we start from a data dependency analysis and define a data dependency graph with the goal to get a deeply pipelined implementation. In this approach, the challenge is the distribution of local on-chip memory close to the implemented arithmetic blocks in such a pipelined fashion. We compare this with an implementation using a data-flow programming approach like MaxJ from Maxeler, where an algorithm is described as a synchronous data-flow graph and implemented as a deep pipeline. In addition, we discuss the local memory distribution using the Maxeler data-flow approach compared to the Xilinx HLS approach.