Dresden 2020 – wissenschaftliches Programm

Die DPG-Frühjahrstagung in Dresden musste abgesagt werden! Lesen Sie mehr ...

Bereiche | Tage | Auswahl | Suche | Aktualisierungen | Downloads | Hilfe

CPP: Fachverband Chemische Physik und Polymerphysik

CPP 12: Focus: High-resolution Lithography and 3D Patterning (Part I) (joint session KFM/CPP/HL)

CPP 12.5: Hauptvortrag

Montag, 16. März 2020, 11:20–11:50, TOE 317

Shapeable materials technologies for high resolution patterning of 3D microelectronic devices — •Daniil Karnauschenko — Institute for Integrative Nanosciences, Leibniz IFW, Helmholtz str. 20, 01069 Dresden, Germany

Electronic devices are continually evolving to offer improved performance, smaller sizes, lower weight, and reduced costs, often requiring state of the art manufacturing and materials to do so. An emerging class of materials and fabrication techniques, inspired by self-assembling biological systems shows promise as an alternative to the more traditional methods that are currently used in the microelectronics industry. Mimicking unique features of natural systems, namely flexibility and shapeability, the geometry of initially planar microelectronic structures can be tailored. Heavily relying on cylindrical geometry, fabrication of microwave helical antennas, coils, resonators and magnetic sensors is challenging, when conventional fabrication techniques are applied. Involving high resolution lithographic patterning and self-assembly strategies realization of these spatially non-trivial devices in a compact form and with a reduced number of fabrication steps become feasible. This spatial self-assembly process, triggered by an external stimulus, offers a possibility of an improved performance while reducing overall manufacturing complexity of devices and components by harnessing the relative ease in which it can produce microscopic 3D geometries such as a *Swiss-roll* architecture. These benefits can lead to tighter a system integration of electronic components including active electronics with reduced costs fabricated from a single wafer.