Die DPG-Frühjahrstagung in Dresden musste abgesagt werden! Lesen Sie mehr ...
Bereiche | Tage | Auswahl | Suche | Aktualisierungen | Downloads | Hilfe
HL: Fachverband Halbleiterphysik
HL 64: Poster II
HL 64.10: Poster
Donnerstag, 19. März 2020, 10:00–13:00, P1A
Fabrication and electrical characterization of top-gated RFETs — •Sayantan Ghosh, Muhammad Bilal Khan, Artur Erbe, and Yordan M. Georgiev — Helmholtz-Zentrum Dresden-Rossendorf, 01328 Dresden, Germany
Following Moore’s Law, the idea of "Beyond CMOS" came into picture, which incorporated emerging research and technology. One such idea is the reconfigurable field effect transistor (RFET). An RFET can be dynamically programmed to p or n polarity by the application of electrostatic potential. This is a silicon nanowire (SiNW) based transistor with two gates - one is used to tune the device polarity while the other modulates the flow of charges. In this work, SiNWs were fabricated using electron beam lithography and inductively coupled plasma etching. Subsequently, optimization of oxide shell/gate dielectric around the nanowires was carried out for better control over the conduction of charge carriers. Afterwards, nickel was deposited at both ends of the nanowire and flash lamp annealing was performed to create NiSi2-Si-NiSi2 Schottky junctions. In the next step, two top gates will be fabricated on the junctions followed by electrical characterization of device parameters. Such novel devices have the prospect of establishing efficient circuits and systems.