SMuK 2021 – scientific programme

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HK: Fachverband Physik der Hadronen und Kerne

HK 11: Instrumentation IV

HK 11.4: Talk

Tuesday, August 31, 2021, 15:00–15:15, H4

Designing FPGA Readout Firmware with the help of Vivado HLS — •David Schledt for the CBM collaboration — Infrastructure and Computer Systems in Data Processing, Frankfurt, Deutschland

Traditionally FPGA firmware was developed solely with Hardware Description Languages (HDL) like verilog or VHDL. However, with the steady improvements of tools like Vivado HLS (High Level Synthesis) it is now possible to write parts of the firmware with higher level languages like C++. Using HLS allows faster development cycles, easier code reuse and, most importantly, to efficiently write complex algorithms for the FPGA.

The Compressed Baryionic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR) will investigate the QCD phase diagram at high net-baryon densities. The experiment employs a free streaming data acquisition with radiation hard self-triggered front-end electronics (FEE). At interactions rates of up to 10 MHz the readout firmware has to process very high data loads. The detector data is marked with timestamps by the FEE, which has to be sorted in time to speed up the online event finding. This requires complex data processing inside the FPGA. In this talk I will present how the readout firmware for the CBM Transition Radiation Detector (TRD) was developed aided by Vivado HLS.

This work is supported by BMBF-grant 05P19RFFC1.