Mainz 2022 – wissenschaftliches Programm

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HK: Fachverband Physik der Hadronen und Kerne

HK 15: Instrumentation V

HK 15.4: Vortrag

Montag, 28. März 2022, 17:00–17:15, HK-H4

Developing Feature Extraction Algorithms with Vivado HLS for the CBM-TRD — •David Schledt — Infrastructure and Computer Systems in Data Processing, Frankfurt, Deutschland

Traditionally FPGA firmware was developed solely with Hardware Description Languages (HDL) like Verilog or VHDL. However, with the steady improvements of tools like Vivado HLS (High Level Synthesis) it is now possible to write parts of the firmware with higher level languages like C++. Using HLS allows faster development cycles, easier code reuse and, most importantly, to efficiently write complex algorithms for the FPGA.

The Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR) will investigate the QCD phase diagram at high net-baryon densities. The experiment employs a free streaming data acquisition with self-triggered front-end electronics (FEE). At interactions rates of up to 10 MHz the readout firmware has to process very high data loads. The CBM Transition Radiation Detector (TRD) is equipped with the SPADIC front-end ASIC. The SPADIC allows for an oscilloscope-like sampling of the detector signals. From the sampled signal several different features can be extracted, such as the deposited charge or a time resolution above the pure sampling frequency. In this talk I will present how different feature extraction algorithms were implemented in the FPGA with Vivado HLS.

This work is supported by BMBF-grant 05P21RFFC3.