Berlin 2024 – wissenschaftliches Programm
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HL: Fachverband Halbleiterphysik
HL 13: Poster I
HL 13.53: Poster
Montag, 18. März 2024, 15:00–18:00, Poster E
Trench-etched In-Plane-Gate Transistors: Fabrication, Characterization, Logical Gates and Simulation — •Lennart Anderson1, Phil Badura1, Matthias Kroll2, Benjamin Feldern1, Arne Ludwig1, and Andreas Wieck1 — 1Angewandte Festkörperphysik, Ruhr-Universität Bochum — 2Experimental Physics IV - Solid State Physics, Ruhr-Universität Bochum
In contrast to conventional field effects transistors (FETs), in which the channel is modulated by a perpendicular electric field, in the In-Plane-Gate transistor (IPGT) gate and channel (and hence source and drain) are in the same plane, leading to a lateral field effect and hence to a two-dimensional system.
In GaAs/AlxGa1−xAs high electron mobility structures conducting channels were defined in a two-stage wet chemical etching process. Current-voltage measurements show characteristic transistor behaviour. A NAND gate is realized based on a single IPGT, showing clear input-output characteristics. Interconnecting several NAND gates, all further basic logical gates, i.e. AND, OR, NOR, XOR and NOT, are realized. The IPGT structure is modelled in nextnano++, and its band structure is obtained by solving the self consistent Schrödinger-Poisson equation numerically. The effect of geometric parameters, i.e. trench width and channel width, as well as the applied gate voltages on the band structure and hence the transistor behaviour is studied. We find that surface states have a significant influence and provide a simple electrostatic model.
Keywords: In-Plane-Gate transistor; Current-voltage charactersictics; Logical gates; Semiconductor device modeling; Surface states