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QI: Fachverband Quanteninformation

QI 7: Quantum Error Correction

QI 7.9: Talk

Monday, March 18, 2024, 17:15–17:30, HFT-TA 441

Scaling Hardware-Based Quantum Error Correction via a Multi-Context Approach — •Jan-Erik Reinhard Wichmann, Maximilian Jakob Heer, and Kentaro Sano — RIKEN Center for Computational Science, Kobe, Japan

The theory of quantum error correction is generally well understood, though its practical implementation remains challenging. This is due to the low-latency requirements for the classical computations that are required to carry out the quantum error correction. Recent advancements have shown that it is possible to meet these latency requirements for surface codes using algorithms implemented in FPGA hardware, but the issue of growing hardware resource consumption persists.

A commonly suggested approach is to distribute the error correction algorithm across multiple FPGA chips. However, the incurred communication overhead runs counter to the latency requirements and will cause the so-called exponential backlog problem.

Here we thus present a different way to reduce hardware resource consumption by using a multi-context approach, trading hardware resources for execution time. By repeatedly saving and loading parts of the error decoder in memory, we can overcome the size limits of a single FPGA. This allows for the simultaneous treatment of larger qubit numbers for higher code distances and even lattice surgery operations, which has remained a difficult challenge so far. The technique we are presenting is developed with our own variant of the Union-Find algorithm in mind but is sufficiently general to be used with all algorithms which work on decoder graphs with limited connectivity.

Keywords: Quantum Error Correction; Surface Code; FPGA