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HK: Fachverband Physik der Hadronen und Kerne

HK 50: Instrumentation XII

HK 50.2: Talk

Wednesday, March 13, 2024, 18:00–18:15, HBR 19: C 1

A FLES Interface Module for the CBM Common Readout Interface Card — •Dirk Hutter for the CBM collaboration — Frankfurt Institute for Advanced Studies, Goethe University, Frankfurt, Germany

The CBM First-level Event Selector (FLES) is the central data handling and event selection entity of the upcoming CBM experiment at FAIR. Constructed as a scaleable high-performance computing cluster, it is designed for online analysis of unfiltered physics data at rates exceeding 1 TByte/s.

Data from the detector systems enters the FLES via custom FPGA PCIe boards, the common readout interface. As part of the FPGA design, the FLES interface module (FLIM) implements the interface between subsystem-specific readout logic and the generic FLES data handling. It receives packaged detector messages and performs data transfers to the host’s memory via a low-latency, high-throughput PCIe DMA engine. The custom design enables a true zero-copy data flow.

The first version of the FLIM is fully implemented and is in active use in CBM test setups as well as the FAIR Phase-0 experiment mCBM. The upcoming second generation of the FLIM optimizes the data flow and is designed to work with the next-generation interface card. An overview of the FLES input interface, performance studies, and plans for the next-generation FLIM will be presented.

This work is supported by BMBF (05P21RFFC1).

Keywords: FLES; DAQ; readout; DMA; PCIe