Karlsruhe 2024 – scientific programme

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T: Fachverband Teilchenphysik

T 117: Trigger+DAQ 4

T 117.3: Talk

Friday, March 8, 2024, 09:30–09:45, Geb. 30.23: 3/1

ATLAS ITk-Pixel Read-out Chain Stress Test — •Matthias Drescher, Jörn Große-Knetter, Arnulf Quadt, and Ali Skaf — II. Physikalisches Institut, Georg-August-Universität Göttingen, Germany

The current ATLAS Inner Detector will be upgraded to an all-silicon Inner Tracker (ITk) for the Phase 2 upgrade of the experiment. The ATLAS ITk readout system uses the FELIX hardware/software system to connect the fibre-optic cables of the on-detector components to the higher-level infrastructure. Each FELIX card has 24 bidirectional high-speed fibre links. In the Pixel subdetector configuration, each uplink fibre is connected to an lpGBT aggregator chip, which in turn bundles 7 Aurora 64b/66b data lanes at 1.28 Gbps. These data are the outputs of the connected front-end chips (RD53A or ITkPix). To ensure stable operation under full load before moving to the final large-scale readout system, a stress test is being prepared populating all 24 FELIX fibres.

Due to limited hardware availability, a stress test setup was prepared using lpGBT and RD53A emulators implemented on several Xilinx FPGA development boards, to be used in place of the respective ASICs. The hit data sent by the RD53A emulators are stored in fast local memory, which can be written from a central controller computer connected to the FPGA boards via Gigabit Ethernet. To implement this Ethernet connection, a processing system is implemented on the FPGA boards, making the design a System-on-Chip (SoC). The project is therefore threefold, consisting of the FPGA design, the SoC processor code and the offline code to control the boards.

Keywords: ITk Pixel; FELIX; FPGA; Emulation; Stress test