Göttingen 2025 – scientific programme

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T: Fachverband Teilchenphysik

T 34: Data, AI, Computing, Electronics IV (DAQ, Detector Electronics)

T 34.1: Talk

Tuesday, April 1, 2025, 16:15–16:30, VG 2.102

FPGA-Based Solution Beyond High-Speed ADCs for Particle Detectors — •Dmitry Eliseev, Erik Ehlert, Carsten Presser, Markus Merschmeyer, Alexander Schmidt, and Thomas Hebbeker — III. Physikalisches Institut A, RWTH Aachen University

Modern particle detector electronics often handle a big number of channels. Field Programmable Gate Arrays (FPGAs) often serve as the core engine of multi-channel acquisition systems. However, the standard approach for acquiring energy or amplitude information for specific events often relies on high-speed multi-channel ADCs. Using such ADCs can increase complexity and raise the cost of signal acquisition electronics. The Multi-Voltage-Thresholding (MVT) method utilizes the internal digital comparators of FPGAs, partially replacing the functionality of ADCs with FPGA-internal resources. This approach enables a fast multi-channel acquisition, which is solely FPGA-based. By eliminating the need for external high-speed multi-channel ADCs, the resulting schematics are simplified, and the cost of the detector electronics is reduced.

This talk explains the MVT methodology and demonstrates its practical application using a 16x16 pixel muon detector with 64 Silicon Photo-Multipliers (SiPMs). The developed system is based on commercially available modules with System-on-Chip (Zynq MPSoC). With compact additional circuitry and developed soft- and firmware, the system features up to 16 high-speed ADC channels, each sampling at 1 GSPS and delivering the sampled data directly to module's RAM.

Keywords: FPGA SoC; High-Speed DAQ; Multi-Channel ADC; DMA; Petalinux